The
purpose of AVSI #17 project is to (1) develop methods
to evaluate mechanisms and accommodate the effects of
accelerated semiconductor device wear out on avionics
system design, production and support, and (2) understand
the nature of progress in semiconductor device technology,
and its impact on the way avionics systems are designed,
produced, supported, and repaired.
Up
to date, the accomplishments of this project include:
-
Analysis of in-service failure data for selected avionics
systems fielded in 1982-2000, and assessment of the contribution
of parts failures to the overall failure rate.
l Identification of the main silicon wearout mechanisms
of current and future semiconductor devices, and description
of the models used to characterize them.
l Development of generic methods to improve the life of
future semiconductor devices by making tradeoffs among
key operating parameters such as speed, voltage, and ambient
temperature.
These
results have been used to initiate and conduct discussions
with 11 semiconductor device manufactures to identify
options for cooperation between the semiconductor device
and aerospace industries. The goal of this cooperation
is to assure a supply of semiconductor devices that can
be used reliably and cost-effectively in future avionic
system designs.
In
2004, the topics of AVSI #17 project to be investigated
at Microelectronics Reliability Engineering Program in
UMD include:
-
Reliability assessment methods: Propose practical reliability
and lifetime evaluation methodologies for electronic devices
which can be used by avionic systems manufacturers.
-
New technology device modeling: Develop verified reliability
models of the three major failure mechanisms (EM, HCI
and TDDB) for new technology nodes.
l CMOS scaling effect analyzing and reliability modeling
of different device families including High-density Memory,
Programmable Logic Devices, Analog-to-Digital and Digital-to-Analog
converters, Operational Amplifier and Power devices: estimate
the impact of ever-decreasing device feature sizes on
these device families and establish reliability models
to characterize their reliability behaviors in CMOS scaling.